The problem of adequately testing digital logic circuits has grown substantially more complex over the years with the rapid increase in the complexity of the logic circuits being designed and fabricated. Most modem approaches to this problem involve the use of sequential test generation (STG) systems which are charged with the task of automatically generating a comprehensive test plan for a given sequential circuit design. Such an STG system is provided with a description of the circuit design, typically in terms of its constituent circuit elements (e.g., logic gates and flip-flops) and the interconnections among those elements and to the circuit's primary inputs and primary outputs. The STG system then automatically generates circuit stimuli which, when applied to the primary inputs of a fabricated instance of the given circuit design, will result in a response at the circuit's primary outputs which will identify (with a reasonable degree of certainty) whether the fabricated circuit is operating in accordance with the given circuit design.
Since the number of possible malfunctions which a fabricated circuit may theoretically exhibit is extremely large, STG systems typically perform their task (and measure the quality of their result) based on a fault "model" in which only a comparatively small number of possible malfunctions are considered. The most common such model, the "stuck-at" fault model, enumerates the set of malfunctions in which each circuit lead (i.e., each input to and each output from a circuit element) may be individually "stuck" at one of its possible values (e.g., logic 0 or logic 1). In this manner, the number of possible faults to be considered is limited to twice the number of circuit leads. The "stuck-at" fault model has become well accepted as providing a reasonable correspondence to the set of likely physical errors which typically result from the fabrication process.
Most STG systems select one of the modelled faults at a time, and attempt to generate tests (i.e., circuit stimuli) which will be able to "detect" that fault. That is, the system's goal is to find circuit stimuli which, when applied to the primary inputs of a "defective" circuit (i.e., one which has the given fault), will result in a response at the circuit's primary outputs which differs from that of a properly operational circuit. Usually, these circuit stimuli am generated as a result of an exhaustive search procedure involving substantial trial and error. For most typical circuit designs, however, quite a few of the faults may be extremely difficult to detect, making STG a very complex and time-consuming problem.
Much of the attention in the field of test generation, therefore, has focused on the problem of circuit "testability." In other words, STG can be made easier by modifying the circuit to be tested so as to improve its testability, without affecting the (normal) operation of the circuit. Specifically, the testability problem can be alleviated by applying certain Design for Testability (DFT) techniques in the circuit design. The two most popular DFT techniques are referred to as "full scan" and "partial scan" design. Using full scan, all the circuit flip-flops are replaced by scanable flip-flops which are connected so as to operate like a shift register during testing. In partial scan, only a subset of the flip-flops are transformed into scan flip-flops, reducing the fabricated circuit area overhead and possibly avoiding delay penalties by not scanning the flip-flops on the critical paths. But in many circuits, a large fraction of flip-flops need to be scanned to achieve a high fault coverage, and in synthesized circuits, a large percentage of paths are critical. Moreover, an expensive sequential test generator needs to be employed. Another drawback of scan techniques is the large test application time, resulting from the fact that every test vector to be applied needs to be scanned in through a series of flip-flops.
Recently, several DFT techniques based on controlling the clock have been proposed. For example, in V. D. Agrawal, S. C. Seth, and J. S. Deogun, "Design for Testability and Test Generation with Two Clocks", Proc. 4th Int'l. Symp. on VLSI Design, pp. 44-51, January 1991, the flip-flops are partitioned into two groups controlled by independent clocks during testing. That is, while the common flip-flop clock remains commonly operable during normal circuit operation, the flip-flop groups may be independently clocked when the circuit is in a test mode of operation. In K. L. Einspahr, S. C. Seth, and V. D. Agrawal, "Clock Partitioning for Testability", Proc. 3rd Great Lakes Symp. on VLSI, pp. 42-46, March 1993, the above concept is generalized to multiple groups. Specifically, the flip-flops are divided so that flip-flops in a loop (of length greater than one) are split between two or more groups. The main advantage of this method is that global feedback can be logically cut by keeping the corresponding clock inactive. However, this technique is inconsistent across circuits, because it targets only their cyclic structure. Moreover, it is not applicable to circuits having only self-loops. And in K. L. Einspahr, S. C. Seth, and V. D. Agrawal, "Improving Circuit Testability by Clock Control", Proc. 6th Great Lakes Symp. on VLSI, 1996, the same authors combine independent clock groups with partial scan to achieve full controllability for all flip-flops.
In S. H. Baeg and W. A. Rogers, "A New Design for Testability Method: Clock Line Control Design", Proc. Custom Integrated Circuits Conf., pp. 26.2.1-26.2.4, 1993, the flip-flops are also partitioned into different groups with independent clocks during testing--however, in this case, all flip-flops within a loop are kept in the same group. Thus, test generation is simplified because there are no loops among groups. Unfortunately, there are several drawbacks to this approach. On the one hand, if the circuit has many self-loops, the number of partitions increases and thus the area overhead and test application time increase proportionally. On the other hand, the presence of a loop covering all flip-flops results in no partitioning at all, making the technique inapplicable. Because of the partitioning objective, the designer cannot control the amount of DFT that can be applied. Also, a specialized test generator is necessary to take advantage of the partitioning.